Signal Integrity Analysis List

2017-06-30 by:CAE仿真在線來源:互聯(lián)網(wǎng)

Hi all,

Is there any general check-list for SI analysis (that has to be taken care while doing pre-route, post-route and si-validation) that available on the net or in this group?

thanks in advance,

Siva

Hi Siva:

Your question encompasses a broad topic; and my responsewill serve only as a partial answer.

Pre-route and post-route procedures although different, check lists can be prepared for both these simulation types. For instance, There are several considerations related to the net groups, topology, themodels, tools, and methodology as outlined below.

I.The BUS/ NETLISTS.

It is often unnecessary to simulate every bus of high speed PCB or every net of a bus. Therefore, simulation effort can be saved by listing those buses/nets to be simulated. Also, distinguishing the signal groups represented( e.g. data, address, control, clock, etc.), their type( single ended, differential) and operation frequencies.

II.TOPOLGY.

Several questions deserve to be addressed regarding topology of each critical net, such as:Is topology point to point? Symmetric?What kinds of drivers/ receivers exist? Are there any connectors? Any terminators on the net?....

III.SIMULATION TYPES/TOOLS

What simulation types (for example:single board,multi-board/ hierarchical, post-route, pre-route, what-if, Monte-Carlo) are to be performed?by what tools( HSPICE, XTK, SpectraQuest, ICX, ...)?

IV.The MODELS.

Modeling issues demand careful attention.What models are needed and in what format (i.e. IBIS, SPICE, Quad,...)? Have these models been tested in previous simulations? Do they require validation?Model evaluation should not be limited only to drivers and receivers; but should encompass all components on the net such as diodes, connectors, resistors, etc. Furthermore, models are frequently needed for different simulation corners including Fast, Typical and Slow.

V.OBJECTIVES.

Before launching simulations, the aims should be well defined and ascertained what SI effects( overshoot/ undershoot, ring back, crosstalk, setup/ hold timing violations, loss, etc.) are being investigated?It is beneficial to examine why simulation is necessary and can alternative approaches such as lattice or Bergron diagrams be utilized.

During the planning phase of a simulation task, it is also helpful to define how many simulation runs need to be carried out and what parameters are to be varied in each run.Trace velocity( or its reciprocal propagation delay) and impedance are frequently among such variable parameters. As an example, the trace impedance for a PCI bus can assume values of 54, 60 and 66 Ohms for the slow (worstcase), nominal and fast (best case) simulation runs respectively.

In closing, check lists can be constructed for pre-route and post-route simulations associated with topology, the models, tools, methodology, objectives, and so on.

Such check lists can prove useful in ensuring that the simulation task is completed accurately and efficiently.

I hope you find this writing informative.

Happy Holiday!

Abe Riazi

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