[SI-LIST] PCIe differential and common impedances

2017-06-30  by:CAE仿真在線  來源:互聯(lián)網(wǎng)


Hi experts!

I have a few queries regarding PCIe Gen3/4 channel impedance.

1. If the recommended differential PCB trace impedance is 85ohms, what should be the common impedance of the traces? if it's 25ohms then tightly coupled differential pair is mandatory.

2. In that case, which termination values would be considered as optimal at the receiver/transmitter to account for minimum common and differential reflections? (assuming we have a singleresistor to power/ground per single trace)

Thank you,

Boris.



Boris,

There isn't a solid rule.

You have to engineer it for the environment you are in and make tradeoffs when necessary. My advice: Eliminate modeconversion as much as possible.

Be watchful of a mixture of large common and/or differential signal discontinuities in the presence of "small tomoderate" amounts of mode conversion. This can lead to high Q resonances in your SDD21 if the residual mixed mode signal is rattling around converting back and forth aka ISI. Not to mention the other problems with it.

As for your termination from a high speed perspective, there are many styles for different situations. You should care about what is most important to your channel and eliminate "unwantednoise" from being generated, if you catch my drift. If you've never used QUCS, you can do nested parametric sweeps with built-in component models or imported touchstones which is handy for looking at potentially thousands of different situations at once.

Best Regards,

Ryan



Boris,

A few signaling standards have bothdifferential and common-mode impedances specified, but many dont.

This provides the freedom for the user toset it according to local circumstances.

These two impedances -as you point out- are related to the coupling strength in the differential pair. If you search thearchives, you will see that this topic has been debated multiple times, it might be useful to look through past comments. As a brief summary, in scenarioswhere the entire path is on the same board with no or just a few tight spots to route through and the cross section is relatively spacious, loosely coupled traces are generally preferred and work better. On high density boards with big via arrays to route through, more tightly coupled traces work better. In these days many of the terminations are provided on the silicon. On the transmit side they are just single-ended driver impedances. At lower frequencies there are simple ways to provide correct termination for both modes: differential clock circuits often have PI or T termination network that simultaneously provide the correct termination for both modes. At higher speeds its effectiveness is diminishing because in the return loss we have to fight the higher frequency discontinuities and the static termination accuracy matters less.

Regards,

Istvan Novak

Oracle



Hi,

Thank you for your explanations. All the above considerations are familiar to me. I am more interested to know how the PCIe specification addresses this topics since it is not brought up explicitlyin the electrical spec (especially the common mode impedance). Thank you again!

Boris.



Boris,

If you are asking how this is addressed in the spec, I think the answer is that the spec purposely does not address this question. Addressing it by specifying the common-mode impedance would limit the implementation choices and addressing it by explaining the various options and trade-offs would go way beyond the scope of the spec.

But to your point, in signaling standards where differential-mode impedance is specified but common-mode impedance is not, it would be good to have a sentence or two saying why it is not specified.

Regards,

Istvan Novak

Oracle




Hi Istvan,

That's exactly right.

When the specification calls for a Common Mode return loss mask for channel compliance, I need to be sure to which port impedance this should be referenced to - 25ohm? 21.25ohm (85ohm/4)?

Boris



Boris,

This is a somewhat different question and on this we are in full agreement: the specification should tell the user what is the normalization impedance. On the other hand, when the return loss spec is -6dB, this means that the channel impedance magnitude can be any where from one third to three times the reference impedance. With 25 ohm you get a range of 8 to 75 ohms, with 21.25 ohms you get arange of 7 to 63 ohms, so even if you take the 8 to 63 ohm common set, it is aquite wide range.

Regards,
Istvan Novak
Oracle


Hi Istvan,
Indeed, -6dB is very relaxed number to comply with.
Thank you for your inputs!

Boris


開放分享:優(yōu)質(zhì)有限元技術(shù)文章,助你自學成才

相關(guān)標簽搜索:[SI-LIST] PCIe differential and common impedances ansysem電磁培訓班 ansys SIwave培訓課程 ansys maxwell hfss培訓和分析 ansysem在線視頻教程 pcb 封裝分析仿真 Fluent、CFX流體分析 HFSS電磁分析 Ansys培訓 Abaqus培訓 Autoform培訓 有限元培訓 

編輯
在線報名:
  • 客服在線請直接聯(lián)系我們的客服,您也可以通過下面的方式進行在線報名,我們會及時給您回復電話,謝謝!
驗證碼

全國服務(wù)熱線

1358-032-9919

廣州公司:
廣州市環(huán)市中路306號金鷹大廈3800
電話:13580329919
          135-8032-9919
培訓QQ咨詢:點擊咨詢 點擊咨詢
項目QQ咨詢:點擊咨詢
email:kf@1cae.com